1. Field of the Invention
The present invention relates to an apparatus of controlling supply of device drive clocks, more particularly, to an apparatus of controlling supply of device drive clocks to supply device drive clocks individually to only operative devices among all devices connected to a data bus in a computer.
2. Description of the Related Art
FIG. 1 is a block diagram of a general portable computer. The portable computer of FIG. 1 comprises a CPU 10 conducting ordinary well-known operations and supervising overall functions; a North bridge 12 conducting both assistant operations of the CPU 10 and management of PCI (Peripheral Component Interconnect) bus, etc.; a video chipset 11, connected to AGP (Accelerator Graphics Port) bus provided by the North bridge 12, for processing video data and outputting the processed data for video presentation; a memory 13 for storing data and programs; a network card 14, connected to the PCI bus, for interfacing the PC and data network; a clock generator 15 generating several clocks to drive other devices; a hard disk drive 17; a disk drive 19 for reading and/or writing data to and/or from a CD-ROM disk or a DVD-ROM disk; a South bridge 16, connected to the PCI bus, for controlling a high storage capacity device such as a hard disk drive and managing an ISA (Industry Standard Architecture) bus; a USB (Universal Serial Bus) controller 18 for communicating with a USB device 20 connected through a USB; a flash ROM 21 connected to the ISA bus; and an I/O chipset 23 and a microprocessor 22 for controlling I/O operations of devices such as a keyboard/mouse 24.
The North bridge 12, connected to the CPU 10 through a host bus 100 as shown in FIG. 1, provides the AGP bus 200 to the video chipset 11 and controls reading/writing operations from/to the connected memory 13. The South bridge 16, connected to the North bridge 12, the network card 14, the clock generator 15, the USB controller 18 and so forth through the PCI bus 300, provides the ISA bus 400 to which the flash ROM 21, the microprocessor 22, and the I/O chipset 23 are connected.
The South bridge 16 has an internal power management module including a device monitoring logic 16a, as shown in FIG. 2, which monitors the states of all devices connected to the PCI bus 300 and makes its one-bit active-low control signal ‘PCI_STP-’ LOW not to supply drive clocks to the devices when the monitored states indicate that they are all inactive.
In addition, the clock generator 15 is capable of supplying its own clock or not in response to the control signal ‘PCI_STP-’. For such a capability, the clock generator 15, as shown in FIG. 2, comprises an internal oscillator 15a producing a reference clock ‘CLK_Ref’ of a desired high frequency; and a clock modulating/selecting unit 15b modulating the speed of the reference clock ‘CLK_Ref’ from the internal oscillator 15a properly for each device connected to the PCI bus 300 and distributing the speed modulated clocks ‘PCI_i’, where i=1 to 5, to the devices.
In detail, the clock modulating/selecting unit 15b, as shown in FIG. 3, includes a plurality of clock modulators ‘CM i’, where i=1 to 5, each of which modulates the speed of the applied reference clock ‘CLK_Ref’ to suitable one which is demanded by a corresponding device or devices. And, each clock modulator selectively outputs its modulated clock ‘PCI_i’ in response to the control signal ‘PCI_STP-’ from the device monitoring logic 16a. 
According to the elements structured as above, when all devices connected to the PCI bus are inactive the device monitoring logic 16a makes the 1-bit control signal ‘PCI_STP-’ active, namely, makes transition from HIGH to LOW. Then, all clock modulators in the clock modulating/selecting unit 15b are disabled by the state transition of the control signal ‘PCI_STP-’. As a result, the drive clocks are not supplied to all the inactive devices unnecessarily.
However, if any one of the devices connected to the PCI bus is operative, the drive clocks are all supplied to not only the operative device but also other inactive devices. Such drive clock supply to the operation-suspended devices causes unnecessary power consumption.